1. Field of the Invention
The present invention relates to an electrically writable-erasable nonvolatile semiconductor memory element.
2. Description of the Prior Art
A floating gate avalanche injection-type MOS (hereinafter referred to as FAMOS) has been placed in practical use as an electrically programmable MOS-type nonvolatile memory. Among the FAMOS's, the two-layer gate-type nonvolatile memory which is usually used as an N-channel element, comprises a source region and a drain region formed on one surface of a semiconductor substrate having one conductivity type, the source and drain regions having a conductivity type opposite to that of the semiconductor substrate, a first insulating film formed on a channel region which is located between the source region and the drain region, a floating gate which is formed on at least a portion of the first insulating film and which is electrically floated, a control gate formed on the floating gate via a second insulating film, and a high impurity concentration region formed on a portion of the channel region and having the same conductivity type as that of the substrate. With the above device, the source region and the substrate are maintained at ground potential, and a positive voltage is applied to the drain region and to the control gate. Most of the drain voltage is consumed in a depletion region in the vicinity of the drain region, where a high electric field is maintained, whereby hot electrons and hot holes are generated due to the avalanche in the high impurity concentration region formed in a portion of the channel region. The hot electrons are injected into the floating gate beyond the energy barrier of the first insulating film composed of a gate oxide film. With the above device, however, it is necessary to maintain a margin of mask alignment to form the high impurity concentration region on a portion of the channel region. This makes it difficult to make the elements small in size and, further, the high impurity concentration region reduces the channel width so that the read-out speed is decreased.
In order to preclude the above-mentioned defects, Japanese Patent Application No. 8655/77 proposes a method by which the high impurity concentration region is formed on a portion of a region which is in contact with at least one of the two sides that are in contact with neither the source region nor the drain region in the outer periphery of the channel region. The devices produced by the above method permit easier reading than the earlier similar devices. According to the above-proposed method, however, the device is formed in the order of a high impurity concentration region, a thick oxide film of the field region, gate oxide film, floating gate, source region and drain region. Accordingly, impurities in the high impurity concentration region tend to be diffused by the subsequent thermal steps such as formation of thick oxide films and n.sup.+ diffusion, which will be performed at high temperatures for extended periods of time. With the above proposed method, therefore, it is difficult to control the concentrations of impurities and it is also not possible to sufficiently increase the concentrations. Further, since the high impurity concentration region is formed beneath the floating gate, the channel width tends to narrow and the threshold voltage tends to increase. Moreover, the thickness of the gate oxide film should desirably be small to attain high-speed operation. With the above method, however, the impurities are diffused from the floating gate during such a thermal step as n.sup.+ diffusion, causing the insulating properties of the thin oxide films to be degraded. Moreover, according to the device disclosed in Japanese Patent Application No. 8655/77, the floating gate has portions riding on the thick field oxide film on both sides of the channel. This causes the floating gate to be stretched in a direction at right angles to a direction in which the source region and the drain region are connected. To cover the floating gate riding on the field oxide film by means of a control gate via the insulation layer is desirable from the viewpoint of increasing the operation speed of the element. From the viewpoint of the layout, however, the control gate is better wired in a direction connecting the source and the drain. According to the above-mentioned setup, therefore, the width of the control gate tends to increase, causing the necessary areas to increase.
With the above-mentioned FAMOS, the writing can be electrically effected, but the memory must be erased by means of ultraviolet light. In an attempt to make a memory device which electrically effects the writing as well as the erasing and which also precludes the defects of the FAMOS's, there has been proposed a method of implanting ions to a high concentration into the channel after the source region, drain region and a thin oxide film of gate have been formed, followed by the formation of a floating gate. According to this method, it is easy to control the impurity concentration since there is no thermal step that is performed at high temperatures for extended periods of time after the channel has been doped with impurity. However, there still remains a problem resulting from the addition of high concentration impurities in the channel region. Therefore, there is imposed a limit for increasing the concentrations, and further, the implanted ions tend to diffuse in considerable amounts into the gate insulating film to deteriorate the dielectric strength.